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TCMD0110G datasheet

Last post 10-29-2008, 9:45 PM by jojolucky. 0 replies.
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  •  10-29-2008, 9:45 PM 9556

    TCMD0110G datasheet

    TCMD0110G datasheet more detail check from

    http://www.chinaicmart.com/series-TCM/TCMD0110G.html
     

    TCMD0110G
    10 Gbits/s Clocked Modulator Driver

    Features
     Operation to 12.5 Gbits/s NRZ.
     Internal optional retiming flip-flop to minimize output
    data pattern jitter.
     Adjustable output amplitude up to 3 V (RL = 50 Ω).
     Integrated dc level adjustment to –1.5 V
     Complementary data and clock inputs, and data
    output.
     Complete operation and control with single –5.2 V
    power supply.
     28 ps rise and fall time (20%—80%).
     2 ps typical rms jitter (clocked mode).
     Clock disable mode for data feed-through.
     Optional 50 Ω on-chip termination for unused output
    (die form only).
     Single or dual-pin pulse width adjust 80 ps—
    120 ps.
     Available in die form or a 32-pin microlead frame
    package.


    Applications
     Optical transmitters.
     Digital video transmission.
     SONET/SDH test equipment.
     SONET/SDH OC-192/STM-64 transmission systems.
     10.7 Gbits/s and 12.5 Gbits/s forward error correction
    (FEC).
     10G Ethernet 10.3125 Gbits

    Functional Description
    The TCMD0110G has been designed to drive electroabsorption modulators (EAMs), electroabsorption
    modulated lasers (EMLs), Mach-Zehnder (M-Z) lithium niobate modulators, and direct modulated lasers (DMLs) that have a 50 Ω input impedance at speeds up to 12.5 Gbit/s NRZ. For nonclocked applications, a clock disable pin is provided.
    The driver consists of an input buffer, a limiting amplifier, a selectable data retiming section, a pulse width control circuitry, an output buffer with adjustabl modulation level, and a dc offset section to provide a mark level adjustment.
    The output buffer is designed to provide 3 V of modulation to a 50 Ω load at each output. The dc offset adjustment networks provide down to –1.5 V offset (see Figure 7). The dc offset for the unused output can be disabled to minimize power consumption (see Table 1).
    The input data is retimed using an integrated flip-flop to remove incoming pattern dependent jitter. This feature is enabled using a clock select pad (see Table 1). If no clock is available, the
    TCMD0110G can be operated in a nonclocked mode. The unused output can be terminated through the integrated 50 Ω resistor when using the die form of the product (see Table 1).

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